1. Field of Invention
The invention relates to a semiconductor device and the associated manufacturing process. In particular, it relates to a manufacturing method of the selection gate in a split-gate flash EEPROM cell.
2. Related Art
Typically, the data storage media in computers can be separated into volatile and nonvolatile memory. The volatile memory includes the dynamic random access memory (DRAM) and static random access memory (SDRAM). Since the data stored in such memory will disappear immediately after the power supply is interrupted, it is mainly used in temporary data input/output (I/O). The nonvolatile memory can keep the stored data even after the power supply is turned off. Therefore, such memory can be used in various occasions. The nonvolatile memory can be divided according to the access method into mask read only memory (ROM), erasable programmable read only memory (EPROM), electric erasable programmable read only memory (EEPROM), and flash EEPROM.
Since the introduction of the 256K flash EEPROM in 1987, it has gradually become the mainstream of nonvolatile memory. The flash EEPROM is a type of high-density memory that combines the advantages of EPROM and EEPROM. It has the merits of being nonvolatile, rewriteable, high-density, and long-lasting. Therefore, it is ideal for applications in portable computers and telecommunications. Some scholars even predict that the flash EEPROM will start the next semiconductor evolution. We thus see the importance of the flash EEPROM in the semiconductor industry.
Normally, the flash EEPROM can be divided according to the structure into split-gate and stack-gate ones. The data erasing speed of the split-gate flash EEPROM is faster than that of the stack-gate ones. Therefore, the semiconductor industry favors the former. In general, the structure of the split-gate flash EEPROM cell includes: a suspending gate consisted of a gate oxide/polysilicon/oxide structure, a control gate/selection gate, and an inter polysilicon dielectric layer between the suspending gate and the control gate/selection gate. It is called the suspending gate structure because its polysilicon layer does not have any electrical communications with any electrode. The data erasing and writing actions in the flash EEPROM can be achieved by imposing different voltage combinations on the gate, source, drain, and substrate, injecting or moving out electrons from the suspending gate. In order for the split-gate flash EEPROM to operate correctly, the selection ate has to at least cover the distance between the drain (or source) and the suspending gate. That is, an appropriate distance has to be maintained between the drain or source and the suspending gate as the electron channel. If the channel length is too short, short channel effects may happen; while if the channel length is too long, the writing efficiency will be bad.
With the increase in the semiconductor integration, the device sizes have been shrunk down to submicron or deep submicron ( less than 0.35 xcexcm) scales. However, normal operations of the flash EEPROM require an appropriate channel length. Therefore, there is some difficulty in making submicron-scale split-gate flash EEPROM. A new split-gate flash EEPROM structure that allows for a certain channel length in the submicron scales is required.
In view of the foregoing, the invention provides a manufacturing method of the selection gate in a flash EEPROM cell. A selection gate is formed on the trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain an appropriate channel length.
An objective of the invention is to provide a method for making the selection gate of a split-gate flash EEPROM cell. This method is applied to a semiconductor substrate. The semiconductor substrate is formed with a suspending gate structure consisted of at least a gate oxide/polysilicon/first oxide, and a source region. The method includes the following steps. Form a trench on a semiconductor substrate on one side of the suspending gate structure, where the trench is opposite to the source region. Form an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench. Forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Finally, form a drain region in the trench on the semiconductor substrate.
Another objective of the invention is to provide a manufacturing method of a split-gate flash EEPROM. The method includes the following steps. Form a gate oxide layer on a semiconductor substrate. Form a polysilicon layer on the gate oxide layer. Form a silicon nitride layer on the polysilicon layer. Form a trench in the silicon nitride layer and expose part of the upper surface of the polysilicon layer, thereby defining a suspending gate region. Form a first oxide layer in the trench. Form a common source plug between two adjacent suspending gate regions. Perform an etching process to remove the silicon nitride layer and the polysilicon layer and the gate oxide layer that are not covered by the first oxide layer, forming a suspending gate structure. Form a substrate trench in the semiconductor substrate on one side of the suspending gate structure. The substrate trench is opposite to the common source plug. Form an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the substrate trench. Form a polysilicon spacer on the sidewall of the polysilicon dielectric layer as a selection gate. Finally, form a drain in the trench on the semiconductor substrate.
A further objective of the invention is to provide a split-gate flash EEPROM cell structure. The structure includes: a suspending gate structure, an inter polysilicon dielectric layer, a polysilicon spacer, a drain, and a source. The suspending gate structure is formed on a semiconductor substrate and stacked from bottom to top a gate oxide layer, a polysilicon layer, and a first oxide layer. A trench is formed on one side of the suspending gate structure in the semiconductor substrate. The inter polysilicon dielectric layer is formed on the sidewall of the suspending gate structure and the trench. The polysilicon spacer is formed on the sidewall of the polysilicon dielectric later as a selection gate. The drain is formed in the trench next to the selection gate. The source is formed on the semiconductor substrate opposite to the trench.
Not only can the disclosed split-gate flash EEPROM structure effectively reduce the sidewise dimension of the selection gate while maintaining an appropriate channel length, hot ballistic electrons are produced to go along the selection gate channel on the sidewall of the semiconductor substrate trench to the suspending gate. This can improve the data writing efficiency and lower the writing voltage. Therefore, the invention achieves the goal of a high access speed and low power consumption for the split-gate flash EEPROM manufactured in a deep submicron process.